Google completes its open Coral NPU edge-AI architecture and ships compiler v1.0; Synaptics launches the first commercial Coral NPU microcontrollers, the Astra SR200 (200–400 GOPS)

Why it matters

【Key points】

On Oct 20, Google Research said its open edge-AI hardware standard Coral NPU hit three milestones; the same day (12:30 UTC) Synaptics launched the first commercial chips on it, the Astra SR200.

1. With this month's Matrix Execution Unit (Milestone 4), the 32-bit RISC-V architecture is complete: 256 MACs/cycle, up to 1 TOPS, ~10 mW average inference target. Full RTL on GitHub (Apache-2.0).

2. Compiler v1.0: open IREE/MLIR toolchain taking JAX, PyTorch and TensorFlow models to Coral NPU, plus the MPACT simulator and a reference FPGA design.

3. Synaptics Astra SR200 MCUs with second-gen Coral NPU IP: SR210/SR230/SR250 at 200/300/400 GOPS, for wearables, sensors, cameras and industrial devices, with custom DRAM up to hundreds of MB.

4. Boards: new Coralboard SR devkit; the 1 TOPS Coralboard SL is now generally available through DigiKey.

5. VeriSilicon handles implementation and verification; GlobalFoundries is tuning it for 12LP+. Next: a 64-bit architecture and CHERI security.

【Verifiable】

Google Developers Blog: https://developers.googleblog.com/unifying-edge-ai-how-coral-npus-open-standard-brings-portable-energy-viable-intelligence-from-model-to-silicon/

Synaptics press release: https://www.globenewswire.com/news-release/2026/10/20/3384402/0/en/synaptics-launches-the-xmcu-era-with-the-astra-sr200-series-of-multimodal-edge-ai-processors.html

GitHub: https://github.com/google-coral/coralnpu

【Our read】

1. Every edge AI chip ships its own toolchain, so each new chip means re-quantizing and rewriting kernels. Google bets on open hardware plus an open compiler: compile once, deploy across vendors.

2. Production silicon and boards move Coral NPU from research to usable; whether it becomes an edge standard depends on vendors beyond Synaptics.

3. The 1 TOPS, 10 mW and GOPS figures are Google's and Synaptics' design targets and specs, not independent measurements.